1. Technical Field
The present invention relates generally to design rule checking for very large scale integrated (VLSI) circuit layouts. More particularly, the present invention relates to a more efficient density checking method, system and program product for VLSI circuit layouts.
2. Related Art
Very large scale integrated (VLSI) circuit layouts are designed using computer-implemented design systems that allow a designer to generate and physically verify (test) a circuit design before the more expensive manufacturing of the integrated circuit (IC). In order to ensure proper design of an IC, each design system and/or IC format includes a set of design rules that each circuit design must meet. That is, each IC design must pass a design rule check (DRC). One fundamental operation of DRC is density checking. Density checking determines whether design shapes of an IC meet a specific density parameter to ensure, for example, the IC meets desired compactness goals, or enables planarization of the wafer, which allows finer lithography and, provides localized loading during etch operations, thus allowing improved yields.
Density checking is one of the more common design rule checks. As shown in FIG. 1, a standard density checking approach evaluates a section 12 of a target level of an IC design 14 using a window 20. Window 20 is sized to accommodate design rule requirements, which are typically based on a certain area. For example, one common density design rule bases density evaluation on a 25×25 μm window granularity requirement. To evaluate an entire IC design 14, the conventional approach finds all shapes on the target level in window 20, calculates a density for the entire window 20 and then compares the calculation to density design rule limits. A window 20 that includes a violation triggers an error. The process then repeatedly moves window 20 by intervals (e.g., of 3 μm), and calculates density for the entire window 20 at each interval until the entire IC design 14 is considered. No data is saved from each calculation.
Since window 20 is significantly larger than the moving interval (e.g., 3 μm), each new placement of window 20 overlaps a significant portion of its previous location. As a result, analysis of an IC design 14 includes a large number of redundant density calculations. The repetitive calculations are accepted as part of the density checking because it ensures that the desired granularity (25×25 μm) requirement of the density design rule is achieved. Unfortunately, the repetitive calculations also make density checking one of the most time-consuming and resource intensive processes of physical verification of IC designs.
In view of the foregoing, there is a need in the art for a method of checking IC design density that does not suffer from the problems of the related art.